The present invention relates to a method for manufacturing a semiconductor device including a vertical cell transistor structure, and more specifically, to a method for manufacturing a semiconductor device including forming a self-aligned storage node contact without a mask process.
Due to increase of integration of semiconductor devices, a planar area occupied by electron elements included in a semiconductor device has been shrunken. In the case of planar transistors, a channel width of the transistor is reduced to increase the integration of the semiconductor device. Since the channel width is proportional to a drain current, if the channel width is reduced, current transmission capacity of the transistor is degraded. As a result, the planar transistor does not both improve the transistor characteristics and increase of the integration in the transistor.
In order to overcome the limits of the planar transistor, a vertical transistor has been suggested. The vertical transistor includes a vertical gate formed at a side surface of a polysilicon pillar, a source formed in the bottom of the pillar and a drain formed in the top of the pillar.
A channel length of the vertical transistor is not limited by a current exposer and exposing method. The vertical transistor has a shorter channel length than that of the planar transistor because the channel length can be adjusted by regulation of the height of the pillar. Also, the vertical gate is formed at the side surface of the pillar so that the vertical transistor may have a broader channel width than that of the planar transistor. As a result, the vertical transistor has a faster switching ability and a greater power driving ability.
However, when a vertical cell transistor is used in a cell region, bit line contacts such as a bit line contact for connecting a bit line having an active area to a core region, a word line contact of the vertical cell transistor, a gate contact of the transistor formed in a peripheral circuit region and a junction region contact of the transistor formed in the peripheral circuit region have various depths, so that the bit line contacts are not formed by one contact process simultaneously.
The bit line contacts for connecting a bit line located in the bottom of the cell region as an active area type to a core region can be formed by several exposure and etching processes. As a result, the process for manufacturing a semiconductor device using the vertical cell transistor is complicated to degrade yield and increase manufacturing cost.